Digital Design Laboratory
| Development boards and design environment overview. Creation of a first project. |
DDL_1.pdf |
Report skeleton |
| Simple logic functions implemenation. |
DDL_2.pdf |
Lab materials |
| Logic gates. Two level logic, SOP implementation. Logic simplification |
DDL_3.pdf |
Lab materials |
| Combinational circuits 1. (Verilog code writing, simulacion, implemenation) |
DDL_4.pdf |
Lab materials |
| Combinational circuits 2. |
DDL_5.pdf |
Lab materials |
| Arithmetical and logical units. |
DDL_6.pdf |
Lab materials |
| Sequential logic elements: latches, flip-flops (RS, D, T, JK) |
DDL_7.pdf |
Lab materials |
| Counters. |
DDL_8.pdf |
Lab materials |
| Shift registers. |
DDL_9.pdf |
Lab materials |
| Memory and storage. |
DDL_10.pdf |
Lab materials |
| A/D and D/ A converters simulation. |
DDL_11.pdf |
Lab materials |
| FSM design, simulation, implementation. |
DDL_12.pdf |
Lab materials |
| Design, simulation, implementation of a digital system. |
DDL_13.pdf |
Lab materials |
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Verilog.pdf |
Download |
| Laboratory_assignments_Checklist_DDL |
Download |
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| In the laboratory practice, we use the free version of the Xilinx ISE 14.7 development environment called WebPack. The installer can be downloaded from the Xilinx website after registration (Xilinx ISE - Full Installer for Windows (TAR/GZIP - 6.18 GB)). The WebPack (free) licence could be obtained also from the Xilinx product licensing site. The software doesn't work on 64 bites Windows 8, 8.1 and 10. The problem can be solved as is presented here (There are also two youtube links that present the solution), or you can try the programm that can be downloaded from here. |